The present invention relates generally to delay cells, and more specifically to differential delay cells having variable delay.
Continual process and voltage scaling in very large scale integration (VLSI) design introduces significant challenges in the design of circuits such as phase lock loops (PLLs), delay lock loops (DLLs), and delay cells included therein. Increasing frequencies of operation and reducing power supply voltages impose reduced uncertainty margins and tighter design tolerances.
FIG. 1 shows a prior art differential delay cell. Delay cell 100 includes saturated load devices 106 and 108 and voltage controlled resistive (VCR) devices 102 and 104 coupled as parallel load devices to the two legs of a traditional differential amplifier configuration. Delay cell 100 also includes a constant current source 120 operating in saturation. Through the high output impedance of current source 120, the currents in the differential legs of the circuit are largely independent of the power supply voltage or the input common mode voltage.
The combination of load devices 106 and 108 and VCR devices 102 and 104 produce a substantially linear resistance characteristic. The VCR devices are added to the standard differential amplifier configuration to linearize the characteristics of the otherwise saturated load devices. The delay value from the differential inputs to the differential outputs is controlled by changing the bias voltage present on delay control node 130.
Despite the differential nature of the circuit, delay cell 100 displays power supply sensitivity because of the nature of the control of VCR devices 102 and 104. Load devices 102 and 104 are biased by the difference between the power supply voltage on node 110 and the voltage on delay control node 130. If the power supply voltage changes, the bias on VCR devices 102 and 104 changes, and the resistance changes, causing the delay through the differential delay cell to change. As a result, when the power supply voltage changes rapidly, significant jitter can appear on the differential outputs of delay cell 100. Typical approaches to reduce these delay variations include closely coupling the power supply and the delay control node so that noise on the power supply is coupled to the delay control node to reduce the bias variations on the delay control node.
In a phase lock loop, delay cells are typically driven by the output of a loop filter. One known method of closely coupling the delay control node and the power supply is to configure the output capacitance of the loop filter such that high frequency power supply noise is coupled to the delay control node. This can have the undesirable effect of reducing the loop filter bandwidth, which also reduces the bandwidth of the phase lock loop.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an alternate method and apparatus to generate a variable delay.